We were looking for support for our quantum error correction project R-QIP | FPGA. The consortium D-fine, Planqc & QC Design was awarded the contract. Together they will implement a hardware decoder for quantum error correction with quantum LDPC codes.

One challenge is the implementation of the error correction codes in operation on real quantum hardware. So-called hardware decoders, which can recognise and correct errors during the runtime of a quantum algorithm, help here.

The development of fast decoders and their implementation on specific systems is a major challenge and is currently only achieved by a few research groups worldwide. The commercial offer is meagre. To our knowledge, there are currently no European or even German providers. Quantum computers available today are often still too small for quantum error correction. For future quantum computers, however, decoders are key technologies for error-tolerant quantum computing. If they can be successfully developed and commercialised, this would be an important factor for the growth of the German and European quantum computing ecosystem.

In order to close the supply chain gap, we have commissioned the development of a high-performance hardware decoder for the execution of a quantum error correction protocol developed by the DLR team in the R-QIP | FPGA project. The contract for the development has now been awarded to D-fine, Planqc and QC Design, who have not only presented a very solid development concept, but also have the necessary technical expertise for the development of hardware decoders.

Background: Qubits for the calculation, classic hardware for the correction

Typical approaches to quantum error correction utilise many physical qubits in order to generate a few low-error and long-lived so-called logical qubits through redundancy. The actual error correction is created by constantly measuring and correcting spontaneously occurring errors. The decoder is the unit that receives and analyses these measurement signals from the quantum processor, recognises errors and their type and applies them as a correction to the individual physical qubits while the quantum algorithm is still running.

This measurement, analysis and correction of an error takes place under high time pressure – typically, an error must be detected and corrected within one gate time so that a calculation can continue to run without errors. Due to their speed, specialised hardware decoders are therefore necessary, but these must be closely matched to the respective quantum computer and its sources of error.

There are several ways of implementing these decoders. All with their own advantages and disadvantages. The R-QIP | FPGA project focuses on a specific approach – LDPC [[512, 174, 8]] – which will be implemented and tested on a commercially available FPGA. In addition, the consortium will test and benchmark various decoders. The advantage of LPDC is the significantly higher throughput and lower overhead compared to the currently widely used so-called surface codes.

Background: Quantum memory and error correction

The decoder developed in R-QIP | FPGA will generate 128 error-corrected, logical qubits from around 1,000 physical qubits. Strictly speaking, however, this statement currently only applies to storage and not to computing with qubits. The reason for this is that error-corrected gate operations and thus the basis of quantum computing cannot currently be achieved with LDPC codes. However, these gate operations are not necessary for storing qubits, which is why LDPC is used.

Quantum processors can both process and store qubits. The difference lies in whether the qubits are actively manipulated by gate operations (computing) or stabilised by error correction – with minimal further modification – (storage). For industrially relevant applications, robust quantum error correction is essential for both storage and computing.

The processing and storage of qubits can also take place simultaneously and in parallel on a sufficiently large quantum processor. In the future, however, processing and storage are likely to be carried out on different, specialised hardware, as is the case with classical computers. Powerful hardware decoders will play an important role in both cases.

The fact that LDPC codes can also be used for error correction in quantum computing is only a question of time, research and development: the first concepts are already being trialled.

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