Paper: Reducing Quantum Error Mitigation Bias Using Verifiable Benchmark Circuits

Joseph Harris · Kevin Lively · Peter K. Schuhmacher

arXiv · 2026

We present a simple, malleable and low-overhead approach for improving generic biased quantumerror mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmarkcircuits which mirror the application circuit’s native-gate structure and thus noise profile. Thesecircuits can be used to benchmark and mitigate the bias of the underlying error mitigation method,requiring only the application circuit and hardware native gate set. We present two methods forgenerating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and hasno gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE)as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigationmethods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scaleclassical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware.We consider the measurement of both single-site observables as well as two-site correlations alonga one-dimensional qubit chain. We also provide a software package for implementing the errormitigation techniques used in this research.

arXiv (2026)
https://doi.org/10.48550/arXiv.2603.10224

arXiv · Creative Commons BY 4.0